High-Performance Low-Power (hplp) Lab

The High-Performance Low-Power (HPLP) Laboratory is dedicated to research in the area of Very Large Scale Integrated (VLSI) Circuit design. Ongoing research ranges from power-, temperature- and reliability-aware CMOS circuit design to explorations in spintronics and nanoelectronics.


Publications

The faculty and students of HPLP work with each other and people outside the lab to collaborate on numerous publications. These include PhD dissertations, MS theses, undergraduate senior theses, technical reports, books, book chapters, journal papers, magazine papers, conference publications, workshop publications, and presentations.  Below, we have a link to the HPLP Zotero Library which contains direct links to the publications categorized by topic.

HPLP Zotero Library

Please check Prof. Stan's Google Scholar Page for full publications list.

Selected Publications Listing:

Showing 55 items
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Mircea R. Stan, Wayne P. Burleson Bus-Invert Coding for Low-Power I/O IEE Transactions on VLSI, vol 3, pp 49-58, 1995 
Adam C. Cabe, Mircea R. Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM.   ACM Great Lakes Symposium on VLSI 2011: 399-402 
Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Edmund Cheng: Temperature-Aware Architecture: Lessons and Opportunities. IEEE Micro 31(3): 82-86 (2011) 
Adam C. Cabe, Zhenyu Qi, Mircea R. Stan Stacking SRAM banks for ultra low power standby mode operation. DAC 2010: 699-704 
Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan: SRAM-based NBTI/PBTI sensor system design. DAC 2010: 849-852 
Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan FlashPower: A detailed power model for NAND flash memory DATE 2010: 502-507 
Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan Temperature-to-power mapping. ICCD 2010: 384-389 
Mircea R. Stan, Dincer Unluer, Avik Ghosh, Frank S. C. Tseng: Graphene Devices, Interconnect and Circuits - Challenges and Opportunities  ISCAS 2009: 69-72 
Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan Differentiating the roles of IR measurement and simulation for power and temperature-aware design.  ISPASS 2009: 1-10 
Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED 2009: 1-6 
Sudhanva Gurumurthi, Sriram Sankar, Mircea R. Stan Using Intradisk Parallelism to Build Energy-Efficient Storage Systems. IEEE Micro 29(1): 50-61 (2009) 
Sriram Sankar, Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan Sensitivity-Based Optimization of Disk Architecture IEEE Trans. Computers 58(1): 69-81 (2009) 
Zhenyu Qi, Mircea R. Stan NBTI resilient circuits using adaptive body biasing ACM Great Lakes Symposium on VLSI 2008: 285-290 
Wei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron Many-core design from a thermal perspective DAC 2008: 746-749 
Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan Intra-disk Parallelism: An Idea Whose Time Has Come ISCA 2008: 303-314 
Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan Sensitivity Based Power Management of Enterprise Storage Systems MASCOTS 2008: 93-102 
Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model.  IEEE Trans. Computers 57(9): 1277-1288 (2008) 
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan: Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262 
Yan Zhang, Mircea R. Stan: Temperature-aware circuit design using adaptive body biasing. ACM Great Lakes Symposium on VLSI 2007: 84-89 
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan SODA: Sensitivity Based Optimization of Disk Architecture  DAC 2007: 865-870 
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan Multi-Dimensional Circuit and Micro-Architecture Level Optimization.  ISQED 2007: 275-280 
Zhijian Lu, Wei Huang, Mircea R. Stan, Kevin Skadron, John Lach Interconnect Lifetime Prediction for Reliability-Aware Systems. IEEE Trans. VLSI Syst. 15(2): 159-172 (2007) 
Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan Designing CMOS/molecular memories while considering device parameter variations JETC 3(1): (2007) 
Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour Design approaches for hybrid CMOS/molecular memory based on experimental device data ACM Great Lakes Symposium on VLSI 2006: 2-7 
Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron Procrastinating voltage scheduling with discrete frequency sets DATE 2006: 456-461 
Garrett S. Rose, Mircea R. Stan A programmable majority logic array using molecular scale electronics. FPGA 2006: 225 
Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler Hybrid CMOS/Molecular Electronic Circuits. VLSI Design 2006: 703-708 
Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, Mircea R. Stan HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. IEEE Trans. VLSI Syst. 14(5): 501-513 (2006) 
Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan Optimal procrastinating voltage scheduling for hard real-time systems. DAC 2005: 905-908 
Sivakumar Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron Monitoring Temperature in FPGA based SoCs ICCD 2005: 634-640 
Yan Zhang, Travis N. Blalock, Mircea R. Stan: A three-level toggle-avoid bus signaling scheme ISCAS (2) 2005: 1843-1846 
Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan The need for a full-chip and package thermal model for thermally optimized IC designs.  ISLPED 2005: 245-250 
Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron Improved Thermal Management with Reliability Banking  IEEE Micro 25(6): 40-49 (2005) 
Lei He, Weiping Liao, Mircea R. Stan System level leakage reduction considering the interdependence of temperature and leakage DAC 2004: 12-17 
Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy Compact thermal modeling for temperature-aware design.  DAC 2004: 878-883 
Matthew M. Ziegler, Mircea R. Stan A Unified Design Space for Regular Parallel Prefix Adders DATE 2004: 1386-1387 
Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron State-Preserving vs. Non-State-Preserving Leakage Control in Caches. DATE 2004: 22-29 
Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron Interconnect lifetime prediction under dynamic stress for reliability-aware design.  ICCAD 2004: 327-334 
Mircea R. Stan Systolic counters with unique zero state ISCAS (2) 2004: 909-912 
Mircea R. Stan, Yan Zhang Perfect 3-Limited-Weight Code for Low Power I/O PATMOS 2004: 79-89 
Mircea R. Stan, Fatih Hamzaoglu, David Garrett Non-Manhattan maze routing SBCCI 2004: 260-265 
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea R. Stan Power-Aware Branch Prediction: Characterization and Design IEEE Trans. Computers 53(2): 168-186 (2004) 
Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan Large-signal two-terminal device model for nanoelectronic circuit analysis IEEE Trans. VLSI Syst. 12(11): 1201-1208 (2004) 
Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, David Tarjan: Temperature-aware microarchitecture: Modeling and implementation. TACO 1(1): 94-125 (2004) 
Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron Reducing Multimedia Decode Power using Feedback Control  ICCD 2003: 489- 
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan Temperature-Aware Microarchitecture. ISCA 2003: 2-13 
Matthew M. Ziegler, Mircea R. Stan The CMOS/nano interface from a circuits perspective  ISCAS (4) 2003: 904-907 
Mircea R. Stan, Marco Barcella MTCMOS with outer feedback (MTOF) flip-flops ISCAS (5) 2003: 429-432 
Mircea R. Stan, Kevin Skadron Guest Editors' Introduction: Power-Aware Computing IEEE Computer 36(12): 35-38 (2003) 
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan Temperature-Aware Computer Systems: Opportunities and Challenges IEEE Micro 23(6): 52-61 (2003) 
Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron: Alloyed Branch History Combining Global and Local Branch History for Robust Performance. International Journal of Parallel Programming 31(2): 137-177 (2003) 
Mircea R. Stan, Kevin Skadron, Marco Barcella, Wei Huang, Karthik Sankaranarayanan, Sivakumar Velusamy HotSpot: a dynamic compact thermal model at the processor-architecture level Microelectronics Journal 34(12): 1153-1165 (2003) 
Mehdi Kabir, Mircea R. Stan, Stuart A. Wolf, Ryan B. Comes, Jiwei Lu: RAMA: a self-assembled multiferroic magnetic QCA for low power systems.  ACM Great Lakes Symposium on VLSI 2011: 25-30 
Kaushik Mazumdar and Mircea Stan Breaking power delivery wall using voltage stacking GLSVLSI 2012 
M. Sadi, M. Stan, S. Kittiwatanakul, B Percy, J Lu, S,Wolf and R. Weikle Characterizing the Switching Phenomena of the Metal Insulator Transition Material VO2 SRC, TECHCON 2012 
Showing 55 items