Stacked Cores using the idea of charge recycling to power cores
Manifold attractions:Reduction in supply current and off chip IR LOSS, Less number of power pins, more off
chip bandwidth, reduced EMI effects.
Synthesized and simulated PIC16 Micro controller using 65nm technology and used them to emulate the
Taped out 4x4 stacked cores ( with 100s of ROs ) with MITLL 150 nm technology.
Publication: Kaushik Mazumdar and Mircea Stan " Breaking the Power Delivery wall using Voltage
Stacking ", GLSVLSI 2012 http://dl.acm.org/citation.cfm?id=2206795
On Chip Charge recycled power delivery for Sub threshold/Near threshold
Push Pull switched capacitor regulator to support charge recycled power delivery schemes for low power
Flash ADC based regulation scheme for frequency modulation
Efficiency versus Power density trade off analysis between conventional on chip switched capacitor and
charge recycling based regulation
Publication : Kaushik Mazumdar and Mircea Stan, " Charge Recycling On Chip DC-DC Conversion for
Near Threshold Operation ", IEEE SubVt, 2012
All Digital LDO Design for On Chip Voltage Regulation
Hysteresis based digital low drop out regulator designed for on die integrated voltage regulator.
1.5 bit ADC based regulation scheme.
Coarse grain counter to handle large di/dt and fine grain counter to suppress steady state ripple.
Dynamic gain control and adjusting switching phase/frequency of the control block to improve efficiency and
worst case droop performance.
Internship : Summer intern at Intel Circuit Research Lab, Portland, Oregon : Worked on on chip hybrid
regulator providing wide range of voltage for supporting DVFS to a processor core. Was able to high amount
of current at a high efficiency. Developed novel hysteresis based feedack scheme to improve transient
response while minimizing droop and ripple.
On chip switched cap based regulator
On die switched cap regulator with different conversion ratios (1:2, 2:3,1:3) to support DVS per core.
Switching frequency and switch conductance modulation based scheme of regulation
On Chip Voltage conversion using weighted power gating
Improving efficiency of On chip regulation using less number of power modes and extending the
regulation range by usingweighted power gating scheme
3-D IC Power Delivery: challenges and solutions
Several power “walls” that must be overcome in future technologies are the 3-D IC power delivery wall
and the on-chip power regulation efficiency wall. In 3-D ICs, power is consumed in the volume of the 3-
D chip, but can be delivered only to a 2-D surface - as the number of layers in a 3-D IC becomes
larger, the greater the mismatch between 3-D consumption and 2-D delivery. The efficiency of on-chip
regulators, which bounds the overall power efficiency of an IC, is not unique to 3-D, but becomes
essential due to the volumetric nature of the system. This paper studies voltage stacking of multi-layer
heterogeneous 3-D systems with distributed DC-to-DC on-chip regulators. The physical layering of 3-D
IC naturally maps to a voltage stacked solution that overcomes some of the difficulties with voltage
stacking in 2-D, such as isolating the stacked domains from the substrate.
Publication: Kaushik Mazumdar and Mircea Stan, " Breaking the Power Delivery Wall in 3D IC ",
Asilomar conference on signals, systems and computers, California, Nov 2012
Team Members :