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STTRAM

Spin Transfer Torque (STT) RAM

Performance and power are both key figures of merit in the design of the memory hierarchy of modern high-performance processors. While the conventional design approach has been to use a different technology for each layer of the hierarchy (caches, main memory, and storage), an alternative is to use a single “Universal Memory” that embodies the desired properties of all layers. One such candidate is Spin-Transfer Torque RAM (STT-RAM).

STT-RAM bit-cell consists of a magnetic tunnel junction (MTJ) and an access transistor. In this project, we focus on developing a circuit model of MTJ and explore different ways to reduce the high write energy of STT-RAM bit-cell.

 

MTJ Circuit Model

  • Key Features:

Model captures the DC and transient characteristics of MTJ.

DC part of model is based on tunneling current through oxide barrier.

Transient part of model solves the LLG equation.

Intrinsic variation in MTJ is captured using langevin random field.

Model is fully implemented in SPICE and is validated with published results.

 

Write Energy Reduction

  • In this project we are exploring different write energy reduction techniques at the device, circuit and architecture level.

Device Level Techniques

         ·         Low Ms Ferromagnetic material

         ·         Reducing data retention time

         ·         Partial perpendicular anisotropic ferromagnetic material

Architecture Level Technique

         ·         Invert coding scheme

In this scheme, we exploit the asymmetry in write “0” and write “1” energy to decrease the overall write energy.


Funding agency: Grandis & DARPA

Team Members

  • Mircea R Stan
  • Ben Melton
Past Team Members
  • Anurag Nigam