Description : This is a system on chip based project where we have designed and fabricated RF and digital blocks and trying to develop a system level testing method for RF-digital interaction. This project has been funded by SRC (Syracuse research corporation)

Members : Mircea Stan
                 Kaushik Mazumdar

Overall Block Diagram for System


The RF test scheme will be divided into three steps -

Step 1 -

Deciding which package to use;

Collecting fundamental information of the error introduced by the test board.

We prepared 2.4GHz front-end QFN chips and test board for the QFN package. This enables us to measure the error introduced by the test fixture and get a sense of how much it deviates from its datasheet value.

Procedure -

1) 3.5mm SMA receptacles are utilized on the test PC board as input and output interface to the Vector Network Analyzer (VNA).

2) To ensure the accuracy of the test, an open and a short are used to extract out the error contributed by the test board - it is challenging to make a standard through line in this case, but in the next step it would be interesting to build calibration standards on the test board. In this way the error introduced by the board can be subtracted directly when doing measurement.

The idea is that when using VNA to do a measurement, the results contain the response of the device under test, the lines, the connectors and the inside of the machine. When doing calibration with standards, the response of the undesired factors is recorded and will be excluded from the entire response, thus the correct response of the device under test is known.

Such process can be done both by the machine automatically and by person, both will be used to decide which one is more appropriate since the calibration standards we are planning to build on the PC board will not be as accurate as calibration standards.

3) Calibrate the VNA (Using calibration standard)

4) Taking measurements on the VNA and record data

5) Conducting data analysis to find out what is the error introduced by the test fixture as well as how much the test chip deviates from its vendor's datasheet.

Step 2 -

After choosing the package, a specific RF test PC board will be designed for the accurate RF test.

Taking advantage of the on-chip RF probe pads reserved while designing layout of the front-end, the LNA stage and mixer stage can be tested separately at first. Next, the testing of the RF front-end will also be conducted. Procedure will be somewhat similar to the previous step except the testing chip will be mounted on-board and the RF blocks of Project Everest will be characterized.

Step 3 -

The ultimate objective is to integrate both digital and analog (RF) blocks on the same test board and characterize all blocks as a functioning system. The analog portion will be fed in to a commercially purchased ADC. We will likely use an AD7643. In order to implement the Hilbert Transform we will load an appropriate algorithm onto the FPGA embedded on our second test board. We will perform individual tests on these two blocks of the system to ensure they work properly before we integrate them into the entire system.

For the Cordic portion of the system we will be using the older 350nm design rather than the 90nm design. Tests on the 90nm processor provided results that were not consistently accurate enough for us to be confident that the system will function properly. We recently returned to the lab with the 350 nm processor and retested its functionality. All three computational modes of the chip (rectangular to polar, polar to rectangular, and sin/cos) worked exactly as they were designed to work. Every input test vector resulted in the exact expected output test vectors. The tests were performed under a range of clock frequencies and we found that the breakdown frequency is near 35MHz.

Our initial testing will take place across two test boards. One will house the 350nm Cordic and the other will handle everything else. With the entire system connected together, we will perform an extensive set of tests to evaluate the overall functionality of the system. Along the way we will be designing a generic test board that will be able to house the entirety of the system.

Necessary Test Equipment

  • Voltage Sources - Agilent E3630A?
  • Pattern Generator - Tektronix P6470
  • Logic Analyzer - Tektronix TLA714
  • Multimeter - Keithley 2000

Block Specification:

ADC : The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. The part has no latency and can be used in asynchronous rate applications.

Discrete Hilbert/Fourier Transform :The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. There is a DHT alogorithm,coded in VHDL (,hilbert_transformer ) that we plan to use on a FPGA chip.

Cordic chip : Based on 350nm technology,Cordic is a 108 pin chip that performs rectangular to polar co-ordinate and vice versa.It performs at supply voltage 0f 3.3 v at a frequency of 33 Mhz.