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Aging in FPGA Chips

This is a sub-project of CLASH. The idea is to demonstrate the self-healing techniques using commercial FPGA chips. In this work we postulate that future electronics system will use sleep time as an active recovery period essential for their overall performance. Our hypothesis is that by explicitly controlling the ratio of sleep vs. active and sleep conditions (e.g. higher temperatures, negative voltages), we can deeply rejuvenate electronic systems periodically to improve their metrics. We use a series of stress and recovery experiments using commercial FPGAs to demonstrate several cases where we bring stressed chips to within 90% of their original margin by actively rejuvenating for only 1/4 of the stress time. We validate our experiments against extracted models and present potential applications to multicore.

Phase I, 
Model and Demonstrate accelerated self-healing techniques on commercial FPGA chips in 40nm technology node. (DAC' 2014)
Demonstrate accelerated self-healing techniques on custom circuitry (Test chip tapeout on 2/18/2014)
Explore on-chip solution for accelerated self-healing techniques (Test chip tapeout on 2/18/2014)

Phase II, 
Explore other circuit topology aging and recovery
Novel aging sensor will be designed 
Wearout model development
Aging Aware design


Conference Papers:
[1] Xinfei GuoWayne Burleson, Mircea R. Stan, "Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques," Design Automation Conference (DAC)San Francisco, CA, June 2014.(pdf)

[1] Xinfei Guo, Mircea R. Stan, "Exploring Accelerated Self-Healing Techniques for Electronic Chips and Systems," the 10th annual University of Virginia Engineering Research Symposium (UVERS), Charlottesville, VA. March 2014.(pdf)

[1] Xinfei Guo and Mircea R. Stan, "Aging effect in FPGA chips and systems,"  A. Richard Newton Young Fellow Poster Session at Design Automation Conference (DAC)Austin, TX. June 2013.(pdf)

Xinfei Guo,
Jul 16, 2013, 11:58 AM