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Analog Turbo Decoder

As part of the SRC Design Challenge, members of the HPLP Laboratory designed an Analog Turbo Decoder in order the show the performance gains of turbo decoding using a SiGe BiCMOS process.  The design makes use of translinear networks used to multiply arrays of currents for the purpose of performing the decoding algorithm in an analog architecture.

Team Members:
Layout of the chip: