High-Performance Low-Power (hplp) Lab

The High-Performance Low-Power (HPLP) Laboratory is dedicated to research in the area of Very Large Scale Integrated (VLSI) Circuit design. Ongoing research ranges from power-, temperature- and reliability-aware CMOS circuit design to explorations in spintronics and nanoelectronics.


HPLP Researchers are also part of many research centers/Initiative across departments and/or universities. Here are few examples:

HPLP Projects (ordered from Devices level to System/Application level)

Emerging Technology, Spintronics

Reliability (Wearout), Robust Systems

  • NBTI Modeling
  • SRAM PUF

Mixed-signal Design, Analog Circuit

  • High-speed ADCs
  • Analog Computing

Low Power Design, Energy-efficient Design

  • VELVET Chip (Energy Efficient System based on RISC-V core)
  • Asynchronous Circuits
  • FinFET Related Design

3DIC, 3D Architectures

  • 3D NAND Flash

Pre-RTL Design Space, Modeling, Tools

  • RISC5 - Implementing RISC-V ISA in gem5 New!
  • OldSpot - SoC reliability and lifetime simulator  New!
  • High-level Synthesize (HLS)

New Architectures, Automata Processing (AP)


Retired Projects

Research Funding
  • National Science Foundation (NSF)
  • Semiconductor Research Corporation (SRC)
  • DARPA
  • Industry - Intel, AMD, IBM, Micron, etc.

This page is updated on 6/8/2018.