High-Performance Low-Power (hplp) Lab

The High-Performance Low-Power (HPLP) Laboratory is dedicated to research in the area of Very Large Scale Integrated (VLSI) Circuit design. Ongoing research ranges from power-, temperature- and reliability-aware CMOS circuit design to explorations in spintronics and nanoelectronics.


Xinfei's paper is awarded "Best in Session" at SRC TECHCON!

posted Sep 15, 2017, 6:00 PM by Xinfei Guo   [ updated Sep 16, 2017, 9:11 AM ]

Xinfei and Prof. Stan's paper is awarded "Best in Session" at SRC TECHCON 2017 held in Austin, TX. Also another paper co-authored by Xinfei and Prof. Stan got the same award. TECHON is an annual industry conference for students funded by SRC to present their work. With over 400 attendees and 32 sessions at the conference, receiving this award is quite an achievement!

Here are information for both papers. 

X. Guo, M. Stan, "Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery," SRC TECHCON, Austin, TX, September 2017. (Session 20)
M. El-Hadedy, X. GuoW. Hwu, M. Stan, K. Skadron, "Crypt-Pi: A Light and Fast Crypto-Processor for IoT Applications," SRC TECHCON, Austin, TX, September 2017. (Session 12)
The session winners (Photo credit: SRC website)

Alec passed his dissertation proposal!

posted Aug 29, 2017, 7:32 PM by Xinfei Guo

Congratulations to Alec for passing his dissertation proposal titled "Improving Reliability and Security with Aging and Pre-RTL Modeling"!

Welcome new hplp members!

posted Aug 25, 2017, 8:23 PM by Xinfei Guo

In fall 2017, Yunfei Gu and Junhan Han joined as PhD student, Benjamin Ghaemmaghami joined as undergraduate researcher. Welcome to the hplp family!

Paper by hplp members named google scholar classic paper!

posted Aug 25, 2017, 8:11 PM by Xinfei Guo

Google Scholar has designated a paper co-authored by previous hplp members and Prof. Kevin Skadron and his students as a "Classic Paper in Computer Hardware Design for 2006 (3rd most cited paper)." The paper is titled "HotSpot: A Compact Thermal Modeling Methodology for Early-stage VLSI Design." 

Read more here

Prof. Stan presented at the 2017 Stephen and Sharon Seiden Frontiers in Engineering and Science Workshop

posted Aug 25, 2017, 8:07 PM by Xinfei Guo

Prof. Stan presented "Back to the Future: Digital Circuit Design in the FinFET Era" at the 2017 Stephen and Sharon Seiden Frontiers in Engineering and Science Workshop: Beyond CMOS: From Devices to Systems held in Technion, Haifa. The workshop will bring together researchers and executives from academia and industry to discuss the different implications of emerging solid state memories on circuits, systems, computer architecture and the hi-tech industry. The full program can be accessed at http://tce.technion.ac.il/beyond-cmos-program/.

The paper can be found here.
X. Guo, V. Verma, P. Guerrero, S. Mosanu, M. Stan, "Back to the Future: Digital Circuit Design in the FinFET Era," Journal of Low Power Electronics (JOLPE), Vol. 13, No. 3, pp. 338–355, DOI 10.1166/jolpe.2017.1489, September 2017.

Prof. Stan's presentation is available here:

Xinfei awarded the 2017 IEEE CAS Pre-Doctoral Scholarship

posted Jun 11, 2017, 12:35 PM by Xinfei Guo

Xinfei has been awarded the 2017 IEEE Circuits and Systems Pre-Doctoral Scholarship. This highly prestigious recognition is typically given to only two students worldwide each year and recognizes young members enrolled in a PhD program related to the Circuits and Systems Society. More can be found here.
Photo: Xinfei at the ISCAS 2017 Award Ceremony 

Photo: Xinfei and Mircea at ISCAS 2017 award ceremony in Baltimore

Xinfei and Prof. Stan's Paper won the "Best-Of-SELSE" Award

posted Mar 28, 2017, 6:34 PM by Xinfei Guo

Xinfei and Prof. Stan got the Best Paper Award ("Best-Of-SELSE") at the 13th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-13) held in Boston in March. They are also invited to present at a special session in the upcoming IEEE Dependable Systems and Networks (DSN) conference in Denver. 

Xinfei Guo, Mircea R. Stan, "Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery", Proc. of 13th IEEE Workshop on Silicon Errors in Logic–System Effects (SELSE-13), Boston, MA, March 2017.

Xinfei is selected as Featured Reviewer by ACM Computing Reviews

posted Jan 23, 2017, 5:24 PM by Xinfei Guo   [ updated Feb 6, 2017, 7:08 PM ]

ACM Computing Reviews is an ACM monthly journal produced in collaboration with Thinkcloud. Reviewer candidates are evaluated and approved based on many criteria, including educational background and professional experience. Every month, one reviewer is selected as Featured Reviewer among a big reviewer pool based on the quality of the reviews. This month, Xinfei is picked! His featured reviewer's profile is displayed on the site for a one-month period. After that period, it is archived and accessible on the site in our Featured Reviewers area. To access his review profile, please go to http://www.computingreviews.com/browse/browse_reviewers.cfm?reviewer_id=123833

Congratulations to Mehdi for succesfully defending his PhD dissertation!

posted Dec 20, 2016, 5:52 PM by Xinfei Guo   [ updated May 25, 2017, 11:10 AM by Mircea Stan ]

Mehdi succesfully defended his PhD dissertation on "Modeling of Magnetic Spintronic Devices: From Theory to Applications". Way to go! Dr. Kabir!

Prof. Stan gave the keynote talk at SOCC 2016!

posted Sep 27, 2016, 7:38 PM by Xinfei Guo   [ updated Sep 27, 2016, 7:41 PM ]

Here is the link:

Title: "SoX at the Edge: the Heterogeneous, Highly Integrated IoT Systems of the future"
Abstract: Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and closing the energy loop (cooling and power delivery) will punctuate this talk as it explores the challenges and opportunities that IoT systems of the future face as they move away from planar Systems-on-Chip (SoC) to becoming three dimensional Systems-on-Anything (SoX, e.g. Systems-on-Package, Systems-on-Interposer, etc.).

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